Implementation of Low Power VLSI Architecture for Sobel Edge Detection

Abstract

In image processing, the noticeable variations of the image can be found using the edge detection process. This edge detection process facilitates to identify placement and edges of an object. The Sobel edge detection process is preferred since it is simple and more noise immune. Sobel edge detection calculates gradients of a pixel in horizontal and vertical directions concerning neighboring pixels. The gradients absolute quantities are computed, added, and matched to a threshold for finding whether the pixel is an edge pixel or not. In this paper, the Sobel edge detection system VLSI architecture is designed which consumes less power by using the arithmetic blocks like Brent Kung adders. The source image of different resolutions is taken to perform Sobel edge detection and implemented using various FPGA devices by analyzing power dissipation, delay and device utilization summary. Then, simulation, synthesis processes are performed and finally, power analysis is performed using XPower Analyzer of Xilinx ISE software.